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Verilog Design of a Pedestrian Crossing

Verilog Programming

Technical Report 2013 20 Pages

Computer Science - Programming

Excerpt

Contents

Introduction

Session – I
Verilog modules and ‘ucf’ file for session – I
State Diagram of Session – I
Simulation for Session – I
CPLD Fitting Report for Session – I
Working of Program on Coolrunner – II

Session – II
State Diagram for Session – II
Verilog modules and ‘ucf’ file for session – II
Simulation for Session - II
CPLD Fitting Report for Session – II
Working of Program on Coolrunner – II

Introduction

This laboratory results shows the Verilog hardware design language (HDL) and Finite State Machine to control a pedestrian crossing controller and its modification. In session – 1, simple Verilog program is simulated and then tested on Coolrunner – II board. In this session the controller three outside world input which are Clock (CLK), Reset (RESET), Pedestrian (PED) and three output which are Red light (RED), Amber light (AMBER), Green light (GREEN).

In session – 2, some modifications are done on Verilog program used in session – 1 and then again simulated and tested on Coolrunner – II board. In this session the controller 7 segment displays is used to see changes in pelstate, while running modified Verilog program on Coolrunner – II board and Carsensor outside world input has been introduced in modified Verilog program. In this modified Verilog program, number of pelstate has been increased.

This laboratory session provides a good opportunity to learn Xilinx ISE Design Suit software and introduce to Coolrunner – II board.

Session – I

Block diagram of finite state machine of pelican crossing controller used in session – I is shown in figure 1. There are three inputs are given by outside world to FSM controller (pelcont), which is pedestrian, clock and reset. The controller has three outputs red, amber and green light. There is no direct connection between output and input. Two counters (FRTIMER and TIMER) are used to create timer and flash and are fed with clock signal. The TIMER module is used to count long, medium and short time and FRTIMER is used to flash amber light. The clock frequency is 10 KHz.

Abbildung in dieser Leseprobe nicht enthaltenFig 1: Block diagram of pedestrian crossing controller.

Verilog modules and ‘ucf’ file for session – I

Top – level description

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Top level description shows the connection of module pelcont (CON1), FRtimer (FT1), Timer (T1) with each other.

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Test_pelican module is used for simulation. It provides the clock for whole system for simulation process.

FSM pelcont module

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FRtimer module

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Timer module

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Pelicon ucf file

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[...]

Details

Pages
20
Year
2013
ISBN (eBook)
9783656845010
ISBN (Book)
9783656845027
File size
1.3 MB
Language
English
Catalog Number
v284210
Institution / College
Northumbria University
Grade
80%
Tags
verilog design pedestrian crossing

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Title: Verilog Design of a Pedestrian Crossing