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Economies of Scale in Semiconductor Manufacturing

How to Achieve and to Destroy

Master's Thesis 2004 86 Pages

Business economics - Business Management, Corporate Governance

Excerpt

Table of Contents

Preface

1 Introduction into the Semiconductor Industry
1.1 The Semiconductor
1.2 Semiconductor Manufacturing Technologies
1.3 Markets and Applications
1.4 General Semiconductor Industry Economics
1.4.1 The Value Chain
1.4.2 Sourcing Strategies and Supply Chain Constraints
1.4.3 Product and Development Cycles
1.4.4 The Semiconductor Pig Cycle
1.4.5 Porters Five Forces of Semiconductor Business

2 Economy of Scale in Semiconductor Manufacturing
2.1 Economy of Scale - General Principles
2.2 Breakdown of Manufacturing Costs
2.3 Product CostModels and Their Importance
2.4 Capital Costs - Depreciation
2.4.1 Investments
2.4.2 Calculating Capital Costs - The Costing Model
2.4.3 Some Definitions about Tool Availability and Processing Speed
2.4.4 Operating Curves
2.4.5 Capacity Planning
2.4.6 Granularity of Investments
2.4.7 Process Complexity Factors
2.4.8 Tool Complexity Factors
2.4.9 Single Technology FAB’s versus Multiple Technology FAB’s
2.5 Personal Costs
2.5.1 Operators (ProductionWorkers)
2.5.2 Maintenance
2.5.3 Process Engineering
2.6 Material Costs and Payed Services

3 Conclusions

Bibliography

Preface

During my work for semiconductor companies as Infineon Technologies and Austri-amicrosystems I had the possibility to deeply get in touch with semiconductor indus­try and with fabrication lines (FAB’s) being operated at different sizes with different product technologies. Especially benchmarking activity with other semiconductor companies and FAB’s gave me the possibility to understand the mechanisms behind efficiency of semiconductor fabrication lines.

In most of observed cases economies of scale are promised to have a great effect on production costs, which in general is true. However it happens that, especially when benchmarking different FAB’s against each other, smaller FAB’s are not that costly as estimated. Looking at them with magnifying glasses shows up methods how to achieve economies of scale even for smaller fabrication lines. However to understand the difference and the real lever for low manufacturing costs intrinsic analysis are necessary. The details of each of these analysis is property of the companies, however within this thesis I generalized the results obtained in the past and removed lots of numbers and facts, without removing the key message. Thus lots of graphs in this figure show numbers, that either have been turned from absolute to relative numbers or falsified numbers in order not to include any company critical information.

Since understanding semiconductor industry is an intrinsic task, also basic rules of this kind of industry are included inside this thesis. This allows readers from other branches to understand the terminology and to get a good broad picture of this industry, at least for the present decade. Since evolution is very fast, certain things will certainly change along the years, however general truths can be applied anytime.

The general aim of this thesis is not to dig very deep inside a certain FAB effi­ciency problem. It is moreover to enlist a big variety of possible influences blocking efficiencies that are believed to be earned with increasing FAB size. For the detailed few on the single efficiency levers and blockers references are enlisted in the back of the thesis. My personal experience shows that alone with these various detailed scientific papers it is very hard to translate the problems to a level, where they can be approached in real life. I hope this thesis help in understanding the economies of scale levers in the semiconductor industry in an sufficient but easy and convenient way.

List of Figures

1.1 Trends for Semiconductor Technologies
1.2 Crossection through a Semiconductor Chip
1.3 View inside a Semiconductor Wafer Fab (Austriamicrosystems - Un- terpremsttten)
1.4 The Trend goes to Smaller and Lighter Packages
1.5 Semiconductor Manufacturing Flow
1.6 Worldwide Semiconductor Market - Total Revenue.
1.7 Total Revenue distributed across the market segments in 2003. (source: Gartner - Dataquest)
1.8 Total Revenue distributed across the market segments in 2003. (source: Gartner - Dataquest)
1.9 Worldwide Growth of Semiconductor Revenue of the Mobile Phones Market Segment (source: IDC, Berenberg Bank)
1.10 Worldwide Growth of Semiconductor Revenue of the DSL Market Seg- ment (source: Cahners In-Stat)
1.11 Semiconductor and Electronics value per Car (source: Gartner Dataquest)
1.12 Value Chain in the Electronic Industry (source: SEMI, SIA, IC In- sights)
1.13 Picture of a Piece of Raw Silicon. Wafers are sawn out of this bar, get polished and processed by further process steps (source: www.nanowelten.de)
1.14 Stepper Equipment of the Upper Price Range (source: Nikon)
1.15 State of the Art Semiconductor FAB complex at Samsung Manufac- turing (Kiheung and Hwasung; Corea) (source: Samsung)
1.16 Timeline of Development and Production Rampup of a Semiconductor Product
1.17 Technology Complexity Trend for Semiconductors
1.18 Porter’s 5 Forces

2.1 Systematic cost reduction per function unit across the years [6]
2.2 Wafer Manufacturing costs 2003 [6]
2.3 Translating inaccuracy of a cost model into gross profit margin and EBIT inaccuracy
2.4 Accuracy diagram connecting EBIT and gross profit margin accuracy with unit process costing accuracy
2.5 Top 10 capital investors [15]
2.6 Investments Slit by Type [15]
2.7 Investments for the Wafer processing Equipment [15]
2.8 Facility cost trends [6]
2.9 Pre tax income versus utilization for the semiconductor industry [6]
2.10 The relationship between cycle time, throughput, and variability
2.11 Economy of Scale Simulation for a Single Technology FAB
2.12 Relation between Maximum Utilization (FF=3) and Number of Tools per Tooltype
2.13 Number of Tooltypes to Manufacture Several Different Technologies
2.14 Economies of Scale Comparison of a Multiple Technology FAB and a Single Technology FAB
2.15 Cumulated Invest for Different Utilized Equipments and for Single and Multiple Technology FAB’s
2.16 Typical product mix including the amount of revenue per technology and the profit margin for each single technology
2.17 Utilization of Different Sized FAB’s during Market Cycles
2.18 Yearly operator salary per country [11]

List of Tables

2.1 Split of of Manufacturing Costs in Fixed and Variable Cost
2.2 Cost Distribution inside a 12 inch FAB
2.3 Cost Distribution inside 20 year old 4 or 5 inch FAB

Abstract

Economies of Scale is an important effect for manufacturing sites of all kinds. Especially very capital intensive productions with a high amount of fixed costs are focused on this economy of scale effects. However this effect is not monitored nor controlled hard enough to assure its benefits.

This thesis puts light on these economies of scale effects with focus put on semi­conductor manufacturing industry. This manufacturing industry is one of the most invest intensive industries. Further the complexity of the product itself and the very fluctuating and difficult to foresee markets produce a very difficult environment. The first chapter of this thesis describes the semiconductor industry. Starting with a description of the product and the value chain process, the different players in this industry are characterized from raw material suppliers to resellers of electronic goods. The different markets are analyzed in a short way to give a picture of the demands covered by semiconductor products and to give information on the past of these markets and on possible future trends. The attributes of the markets are enlisted showing in most cases high entry barriers, short market windows and a fluctuating market cycles. Long development cycles and increasing complexity of the products give product definition, marketing and product development departments quite high challenges. To summarize the attributes of semiconductor industry an analysis with porters five forces has been done.

Chapter 3 starts with an general definition of economies of scale, but very fast focuses on the semiconductor business and its special demands. Understanding the costs generated by the production of the single products and understanding the distri­bution between capital, personal and material costs is the first critical point, that has to be understood. It is observed quite fas]t, that capital costs are the main driver for economies of scale benefits of larger semiconductor manufacturing sites, called FAB’s. The importance of a correct cost model, which is able to split up the costs correctly is discussed and possibilities to solve this problem are enlisted. Capital or depreciation costs are analyzed in very detail. The main parameter proportional to these costs is capital utilization. The correct measurement of this utilization serves as the basis to understand the causes and effects properly. Hand in hand with utilization goes the throughput speed of the manufacturing line, which can be measured in terms of a flow factor. The relation between utilization and FAB speed is explained with the operation curve theory, showing up the importance of the overall variability (alpha) of the FAB. Key finding is that variability is the main enabler or disabler for economies of scale. Large and in most cases older FAB’s, which have been organically growing for several years, tend to have high complexities in the manufacturing process and thus introduce a high amount of variability. Benchmark results between small, large FAB’s, single- and multiple technology FAB’s proof the findings stated in this thesis. The number of tools of which a tool group consists turns out to be a key parameter. Economies of scale benefit is earned until tool group sized of five tool per group are reached. After this amount of tools a saturation effect is observed. The importance of capacity planning and the difficulties of this intrinsic tasks are discussed. Especially the problems with the granularity of the investments when ramping up a very small FAB are highlighted. Diseconomies of scale are normal to occur for these small FAB sizes, when invests on expensive tools are done. Reducing the number of tooltypes inside the FAB is a key measure in this thesis. However also the market risks of too low diversification of various markers are observed as possible problem, when reducing tooltypes and technologies. A single product or technology FAB may thus be very efficient and show great economies of scale effects, however the market for this prod­uct will not be as stable as required to earn these benefits. After analysis of capital costs also personal and material costs are analyzed. Most of the costs show the same sensitivity on the complexity inside the manufacturing line. Regarding personal costs especially the benefit of highly automated FAB’s is enlisted as a must have for large manufacturing sites.

The last section summarizes the findings and shows how to implement this found knowledge for two starting scenarios. The building of a manufacturing site on the green field gives the possibility to account on all important efficiency enables at the very beginning. More difficult is the organization of a change process in a running pro­duction line. Strategies and necessary boundary conditions are enlisted to guaranty success of this change process.

The findings of this thesis are projected on semiconductor industry, however most of the results are although transferable to other manufacturing industries.

Chapter 1
Introduction into the Semiconductor Industry

When more units of a good or a service can be produced on a larger scale, yet with (on average) less input costs, economies of scale are said to be achieved. Alternatively, this means that as a company grows, and production units increase, a company will have a better chance to decrease its costs. According to theory, economic growth may be achieved when economies of scale are realized.

Just like there are economies of scale, diseconomies of scale also exist. This occurs when production is less than in proportion to inputs. What this means is that there are inefficiencies within the firm or industry resulting in rising average costs.

Especially in semiconductor manufacturing, where fixed costs are enormous, these EOS (economies of scale) play a major role. Companies are either growing, merging or disappearing. It seems as in the end there will only be a view players left. But will the economy of scale promises really hold and decrease manufacturing cost as expected? Lot’s of big semiconductor production plants, called FAB’s, already have reached sizes taking about 2 billion USD invest and employing 2000 to 3000 employees. However, when benchmarking these big FAB’s with smaller FAB’s (sized about a factor of ten smaller), the cost gap is not that big as calculations would predict. This means that certain economies of scale cost saving have not been achieved by the large FAB’s.

The reason for this is not found at a single source, but is distributed across the whole manufacturing site and moreover extends to product development and business processes inside the company.

This thesis enlists the major levers to enable economies of scale. First of all, for non insiders of the semiconductor branch the first chapter gives an introduction to this kind of industry.

1.1 The Semiconductor

A semiconductor is a material that is neither a good conductor nor a good insulator. The semiconducting material most commonly used in IC manufacturing is silicon, although gallium arsenide is also used for some applications. In conductors such as metal, electric current is carried by electrons free to wander about the atomic lattice of the material. In insulators, electrons normally stay tightly bound to their atoms and are not available to serve as charge carriers. In semiconductors, free carriers are not ordinarily present, but they can be generated with a modest amount of energy.[17] [2]

Electronic devices are made of active circuit elements such as transistors, and pas­sive elements such as resistors and capacitors. Before the advent of microelectronic technology, these basic functional units were manufactured separately and wired to­gether with metal conductors to form electronic devices. Circuit Elements Micro­electronic technology has not, for the most part, changed the nature of these basic functional units. Rather, it has made these electronic functions more reproducible, more reliable, and less expensive by fabricating miniaturized versions of them on a single semiconducting substrate of silicon or (less commonly) gallium arsenide. As a result, a growing number of logic circuits have been implemented using the basic cir­cuit elements that are most easily fabricated in silicon and perform best: transistors.

Research into some of the mysterious electrical properties of semiconductors led

illustration not visible in this excerpt

Figure 1.1: Trends for Semiconductor Technologies

to the development of the transistor, a device for controlling the flow of electrons in a solid crystal. Such control was previously gained using bulky vacuum tube technology. Transistor technology enabled the reduction of electronic devices to a miniature scale. [7]

For four decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in its products. The principal categories of improvement trends are shown in Figure 1.16 with examples of each. Most of these trends have resulted principally from the industrys ability to exponentially decrease the minimum feature sizes used to fabricate integrated circuits. Of course, the most frequently cited trend is in integration level, which is usually expressed as Moores Law [10] in December 1975 (i.e., the number of components per chip doubles every 24 months). The most signifi­cant trend for society is the decreasing cost-per-function, which has led to significant improvements of productivity and quality of life through proliferation of computers, electronic communication, and consumer electronics.

1.2 Semiconductor Manufacturing Technologies

When a designer conceives of a new product, he or she specifies the functional char­acteristics of the device, selects many of the process steps required to manufacture it, and uses CAD tools to estimate the size and location for the hundreds and thousands

illustration not visible in this excerpt

Figure 1.2: Crossection through a Semiconductor Chip

of circuit elements. So that the goals of the circuit designer will be achieved, a high degree of control over the materials, process steps, and cleanliness of the produc­tion environment is essential during IC fabrication. In IC manufacturing, 100’s to 100.000’s of copies of a microelectronic circuit are simultaneously fabricated on a thin semiconducting substrate–commonly made of silicon–called a wafer. Silicon wafers are typically made by slicing 3 to 12 inch diameter slices, from a purified silicon cylin­der. Silicon cylinders are grown by placing a single-crystal seed in a vat of molten silicon and slowly withdrawing it. Mass production of IC’s is completed in several stages, in which wafers–grouped together in lots of 13-100 wafers–are processed to­gether and converted into the same final product. This process can be summarized in four process stages: wafer fabrication, wafer probe and sort, chip assembly, and final chip test and burn-in. IC manufacturing process stages.

Three important measures of manufacturing efficiency are yield, cycle time and fabrication cost. The costs of the last two stages, chip assembly and final testing, are often higher than wafer fabrication and testing because manufacturing costs are not shared among many die. (A die, or chip, is an individual microelectronic circuit.) Each die must be separately packaged and tested.

Wafer Processing

During wafer fabrication, various layers of substances are formed within the wafer, or deposited on the surface of it in accordance with the plan of the circuit designer. These layers are typically formed in the following way: A thin film of oxide is formed or (less commonly) deposited on the surface of the wafer in a process called oxidation. Then, a photoengraving process called photolithography (also known as ”masking” or ”imaging”) is used to transfer a desired pattern onto the surface of a silicon wafer. Portions of the oxide surface under the pattern are then dissolved away in a process called etching. Finally, in a process called doping, impurities are introduced into the exposed surface to form device elements such as the source and drain of a transistor. Thin films may also be deposited on the wafer to form elements such as the polysilicon gate of a transistor.

These procedures are repeated many times until a complete circuit is is constructed. Wafers are processed in big cleanroom fabs to avoid any contact of dust to the silicon wafers. Figure 1.3 shows a view inside an 8 inch FAB of Austriamicrosystems (Unterpremsttten - Austria)

Wafer Probing

In the second stage of wafer manufacturing, each die on a fabricated wafer is tested for functionality. The dice that fail are marked physically with an ink spot or at newer production facilities an electronic flag is set in the Manufacturing Execution System. The wafer is then sectioned into individual die by scribing lines between the dice and breaking the wafer along these lines. The defective dice are discarded, and the remaining dice are usually sent from the fabrication facility to a die bank

illustration not visible in this excerpt

Figure 1.3: View inside a Semiconductor Wafer Fab (Austriamicrosystems - Unter-premsttten)

inventory. Die lots will be withdrawn from the inventory and assembled when they are scheduled for release. The wafer probe and sorting stage generally takes from a couple of hours up to 2 weeks to complete.

Assembly

In the third stage of wafer manufacturing, die that have been fabricated and tested are assembled for product release. An inventory, called a die bank, of tested die is usually maintained at the assembly plant to smooth out variations in productivity at the wafer fabrication stage. The assembly stage typically takes a few days to several weeks to complete. Review the basic stages of IC manufacturing

Individual integrated circuit die can be mounted in a wide variety of packages. A chip generally assembled by placing it on a (commonly lead) frame, attaching electrical leads to it at contact points (for connections to the outside world), and

illustration not visible in this excerpt

Figure 1.4: The Trend goes to Smaller and Lighter Packages

sealing the assembly in a (commonly plastic or ceramic) protective housing.

Also for assembly technologies are changing quite fast as depicted in figure 1.4.

Die-mounting and wire-bonding is labor intensive and expensive. In fact, the cost of assembly and test can be many times the cost of the fabrication of a small die. In addition, the failure of wire bonds is one of the most common IC reliability problems.

Chip Test and optionally Burn-in

In this final stage, packaged chips are subjected to an extensive series of electrical tests and burn-in operations to ensure that the circuit functions correctly and will continue to do so reliably. (For example, they may be operated for several hours in a high- temperature environment). Final testing and burn-in usually take 1 to 7 days (although burn-in can take up to 5-6 weeks) and are usually done at the assembly plant where chips are packaged. After final test, chips are sorted into different bins based on attributes like device speed and power consumption.

illustration not visible in this excerpt

Figure 1.5 shows the whole semiconductor manufacturing flow.

illustration not visible in this excerpt

Figure 1.6: Worldwide Semiconductor Market - Total Revenue.

1.3 Markets and Applications

The market for semiconductor products is quite huge with total available market volumes above 100 Million Euros. (see Figure 1.6)

This worldwide revenue can be split into market segments as shown in figure 1.7 and described in the next paragraphs.

illustration not visible in this excerpt

Figure 1.7: Total Revenue distributed across the market segments in 2003. (source: Gartner - Dataquest)

PC and IT Market Segment

This personal computer and IT infrastructure market in now in a very saturated state. First time invests have been done in the last years (before 2000) and todays business is mainly controlled by upgrades and by exchanging worn out equipment. The typical exchange cycle for desktop PC’s is 3,5 years and for laptops is 2,5 years. After quite huge Y2K investments, the replacement of these IT investments could be feeled noticed starting from Q2 2003.

A very interesting sub segment of this market is the DRAM (Dynamic Random Access Memory) market. Figure 1.8 shows how the worldwide demand for storage capacity is increasing, however worldwide revenue is drastically decreasing. This is reasoned by an high amount of competition in this commodity business. Demand to stock manufacturing are required to manage to utilize costly wafer production FAB’s also during periods of lower demand. This oversupply of chips in the PC and IT market leads to stock depreciations and further to prices going down.

The rather high sensitivity on price is present throughout the whole PC and IT market. Only for few first months of the market window of a really new product gross

illustration not visible in this excerpt

Figure 1.8: Total Revenue distributed across the market segments in 2003. (source: Gartner - Dataquest)

margins can be kept high. Typical gross profit margins for the DRAM market where negative in the last years.

Summarized, the key attributes of this market are:

- price sensitive
- leading edge technology
- high competition
- saturated market

Mobile Communications Market Segment

Mobile communication covers 11.5 percent of the semiconductor market. This market share can further split up. About 80 percent of this share is taken by mobile phones, 15 percent by infrastructure (e.g. basestations for mobile phone networks and 5 percent other mobile applications (e.g. wireless LAN, bluetooth). Two thirds of the mobile phones sector is purchased by private customers and thus very sensitive on price and fancy features. One major trend for mobile phones is standardization

illustration not visible in this excerpt

Figure 1.9: Worldwide Growth of Semiconductor Revenue of the Mobile Phones Mar­ket Segment (source: IDC, Berenberg Bank)

leading to massive price reduction of these products. The main suppliers of this market segment (Infineon, Texas Instruments, Motorola, Philips) tend to sell not the products but reference designs to Asian manufacturing companies. These are able to supply very cheap mobile phones to Asian markets. Prices are thus decreasing by about 20 to 30 percent per year. The only way to achieve higher prices is to integrate additional functionality into the mobile phone.

Figure 1.9 shows how fast and stable the mobile phone market segment is grow­ing. Since mobile phones are exchanges nearly every year, because new features are supplied, there exists no market saturation effect yet.

Summarized, the key attributes of this market are:

- standardization
- price sensitivity
- strong growth
- high competition
- very short product cycles

illustration not visible in this excerpt

[...]

Details

Pages
86
Year
2004
ISBN (eBook)
9783656038467
ISBN (Book)
9783656040828
File size
3.9 MB
Language
English
Catalog Number
v131348
Institution / College
Donau-Universität Krems
Grade
gut
Tags
economies scale semiconductor manufacturing achieve destroy

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Title: Economies of Scale in Semiconductor Manufacturing